1. Field of the Invention
The present invention relates to a virtualization program, a simulation apparatus and a virtualization method for simulating a multi-task generated on a target OS (Operating System) by means of the native code of a host CPU in a simulation of software including an OS capable of operating for multi-task processing.
2. Description of the Related Art
ISS (Instruction Set Simulation) and native code simulation are known as general computer simulation techniques.
With ISS, a task of the binary code that conforms to the architecture of a target CPU (the CPU of a computer that is the subject of simulation) is interpreted at the time of execution and simulated. With ISS, the simulation of the task takes a long time and hence entire software including the OS cannot be simulated within a realistic time span. With native code simulation, on the other hand, a task of the binary code that conforms to the architecture of a host CPU (the processor of the computer that executes the simulation) is directly executed by the host CPU and hence the task does not need to be interpreted and converted to the binary code that conforms to the architecture of a target CPU so that the simulation can be executed at high speed.
When the target OS (an OS that is the subject of simulation operating on a target CPU) is a multitask OS, the target OS preserves and restores the context of a task by operating a special control register such as the stack register or the PSR (Program Status Register) that the target CPU has to realize context switching for a multitask. The operations of those special control registers are described in the assembler language.
Of the conventional art relating to the present invention, hardware/software cooperative verification methods that can realize a high speed simulation, which is a C-based native code simulation, without degrading the accuracy of timing verification, are disclosed (refer to, e.g., Patent Document 1: Jpn. Pat. Appln. Laid-Open Publication No. 2004-234528). Further, methods of creating a software verification model necessary for executing a process of cooperative verification of hardware/software to be installed in a semiconductor device that can maintain the accuracy level by optimizing the technique of adding a budget process and also improve the performance are disclosed (refer to, e.g., Patent Document 2: Jpn. Pat. Appln. Laid-Open Publication No. 2005-293219).
However, all the software including the target OS needs to be rewritten in the C language to execute a native code simulation.
Additionally, the above-described stack register is not modeled in native code simulators. Therefore, the target OS cannot preserve and restore the context of each task so that, when it executes a multitask, the simulation engine and the target OS need to cooperate tightly to manage the task. The target OS is primarily responsible for management of a task on the target OS. The target OS should operate on a virtual CPU that the simulation engine provides and a task should be executed under the management of the target OS. When the simulation engine and the target OS cooperate tightly to manage a task, the proper hierarchy is not structurally consistent so that the simulation engine needs to be provided with a process for each type of target OS.